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Colloquium prof.dr. Kei Hiraki, University of Tokyo

Tuesday 5 March 2013, 16h00-17h00, lecture room G2.10

http://sne.science.uva.nl/ http://uva.nl/

Talk

On Tuesday 5 March, Professor Kei Hiraki, Department of Creative Informatics, Graduate School of Information and Technology the University of Tokyo, will talk about:
  • Next Generation Japanese supercomputer Project
  • Adaptive TCP congestion control algorithm using multi-layer perceptron.
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Biography

Kei Hiraki is a Professor in the Department of Computer Science, Graduate School of Information and Technology at the University of Tokyo. He received a BA, MS, and Ph.D. in physics from the University of Tokyo. He then worked in the Electrotechnical Laboratory at MITI in Japan from 1982 until 1988. At this time he came to the USA to work at IBM T.J. Watson Research Center. In 1991, he returned to Japan to be a professor at the University of Tokyo.

Prof. Hiraki performed wide range of research Topics including Dataflow architecture, Distributed Shared Memory, Highly-parallel architecture, and very high-speed internet communication. He currently holds all the classes of Internet2 Land Speed Records for high-speed, long-distance TCP communications.

One of his Projects in the past

The University of Tokyo and the National observatory of Japan have been jointly developing a GRAPE-DR system, which realize a combination of Peta-Scale computing and very high-speed data-sharing system for scientific computing. In this talk, we describe the outline of GRAPE-DR project, architecture of the GRAPE-DR processor, and the methods used in Data-Reservoir system which is used to share data among distant research institutes.

Main objectives of GRAPE-DR system are (1) realization of very cost-effective and power-efficient computation, (2) construction of a practical peta-scale computing system for computation-intensive scientific applications. GRAPE-DR adopts different approach, SIMD architecture without interconnects between processing elements(PEs). Figure 1 shows block diagram of GRAPE-DR processor chip. All the data transfer to and from PEs are achieved by broadcasting memory and reduction network with arithmetic units. This architecture is effective to reduce the amount of hardware. As shown in Table 1, the size of the die is much smaller than other chips for HPC systems, such as nVIDIA 8800 or CELL.

GRAPE-DR chip is carefully designed to compute several important applications including n-body problem for galaxy generation, molecular dynamics, quantum molecular simulation (e.g. FMO), dense linear equations (e.g. Linpack), and simulation in bio-informatics.

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