## Colloquium prof.dr. Kei Hiraki, University of Tokyo
Tuesday 5 March 2013, 16h00-17h00, lecture room G2.10 |

## TalkOn Tuesday 5 March, Professor Kei Hiraki, Department of Creative Informatics, Graduate School of Information and Technology the University of Tokyo, will talk about: |
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Prof. Hiraki performed wide range of research Topics including Dataflow architecture, Distributed Shared Memory, Highly-parallel architecture, and very high-speed internet communication. He currently holds all the classes of Internet2 Land Speed Records for high-speed, long-distance TCP communications.

Main objectives of GRAPE-DR system are (1) realization of very cost-effective and power-efficient computation, (2) construction of a practical peta-scale computing system for computation-intensive scientific applications. GRAPE-DR adopts different approach, SIMD architecture without interconnects between processing elements(PEs). Figure 1 shows block diagram of GRAPE-DR processor chip. All the data transfer to and from PEs are achieved by broadcasting memory and reduction network with arithmetic units. This architecture is effective to reduce the amount of hardware. As shown in Table 1, the size of the die is much smaller than other chips for HPC systems, such as nVIDIA 8800 or CELL.

GRAPE-DR chip is carefully designed to compute several important applications including n-body problem for galaxy generation, molecular dynamics, quantum molecular simulation (e.g. FMO), dense linear equations (e.g. Linpack), and simulation in bio-informatics.